Chip integration and netlist generation, cross-team collaboration to implement chip partitioning and floorplan
Synthesis, RTL/netlist quality check, formal verification, function eco creation
Constraints creation and validation, timing budget, work with ASIC team to analyze/resolve function timing issues, achieve all special timing closure, such as io, test, clock, async, etc.
Work in conjunction with PR engineers for chip implementation to achieve full chip timing closure
Develop and improve the entire timing closure flow from the frontend (pre-layout) to backend (post-layout), flow automation development for the above areas
Methodology in any of the above areas
About You
What NVIDIA needs to see:
Currently pursuing a Master's or PhD degree within a relevant or related field
Strong knowledge of IC design
Passionate about technology research and IC backend
Self-driven, good learning ability, good teamwork
Excellent communication skills, proficient in English reading and writing
Ways to stand out from the crowd:
Experience in IC backend implementation
Hand-on experience in EDA software from Synopsys (DC/PT/Formality), Cadence (RC compiler/LEC)
Proficient user of Python or TCL
Benefits
NVIDIA helps interns succeed and grow through comprehensive benefits such as:
Intern Experience
Healthcare Programs
Time Off & Holidays
Well-Being
Learning & Development
Training & Development
As an ASIC-PD intern at NVIDIA, you'll learn and work on the tasks from RTL frozen to tape out, including synthesis, formal verification, constraints definition, timing closure/sign off, study on the timing impact of the process, and related methodology work.
Career Progression
Interns at NVIDIA are employees. They do real work, on real projects, side by side with some of the industry's brightest minds. Interns get hands-on with never-before-seen technologies and the latest software and hardware developments.
How to Apply
NVIDIA hiring process:
Search and apply
Meet
Join the team
Sources
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