ASIC TOP Floorplan Intern (Start ASAP)

Your Role

Key responsibilities as follows:

• Collaborates with architects, design leads, and package leads to develop and optimize floorplans during early chip development.
• Drives the area review process and works with the ASIC design team to identify improvements in area, interconnect, and floorplan.
• Resolves timing and routing congestion issues by influencing early design and physical implementation decisions.
• Builds tools and enhances existing infrastructure to optimize chip area and execution speed.

About You

Ideal candidates will have:

• Pursuing a Master's Degree in Electrical Engineering, Computer Science, or Computer Engineering.
• Experience with CAD, physical design methodologies, chip floorplan, power/clock distribution, packaging, P&R, and timing closure.
• Strong communication and interpersonal skills, with a desire to work collaboratively.
• Proficiency in Python, Perl, and C/C++ programming languages.

Benefits

• Competitive compensation package including health benefits, performance bonuses, and access to cutting-edge technology.

Training & Development

Offers professional development programs and mentorship opportunities to enhance skills and career growth.

Career Progression

Potential for advancement into senior engineering roles, contributing to innovative projects in AI and self-driving technology.

How to Apply

Submit your application with a resume and cover letter detailing your relevant experience and interest in the role.