ASIC Design / Verification Intern (Start ASAP)

Your Role

Key responsibilities are as follows:  

• Collaborate with a mixed-signal design team to design and verify Backplane Ethernet, PCIe, and USB SERDES products. 
• Engage in specification development and perform functional and performance tests on test chips.  
• Work closely with digital and mixed-signal engineers to deliver high-end designs.

About You

The ideal candidate will have:  

• Hands-on experience with Verilog/SystemVerilog.  
• Understanding of high-speed digital and mixed-signal design.  
• Experience in FPGA design and verification.  
• Proficiency in scripting languages like Python and Perl.  
• Strong organizational and communication skills.  
• Knowledge of digital signal processing is a plus.

Benefits

Synopsys offers a comprehensive package including healthcare and other perks.

Training & Development  

Interns will receive mentorship and the opportunity to work on real projects, enhancing their skills and career prospects.

Career Progression 

Successful interns may have opportunities for full-time positions and career advancement within Synopsys, a leader in semiconductor IP.